Микросхема SN74ABT373DW, SO20

Характеристики

SN74ABT373DW, SO20The SN74ABT373DW is an octal transparent D Latch with 3-state outputs. While the LE input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered OE input can be used to place the eight outputs in either a normal logic state or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need for interface or pull-up components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor, the minimum value of the resistor is determined by the current-sinking capability of the driver.

• State-of-the-art EPIC-II BTM BiCMOS Design significantly reduces power dissipation
• Latch-up performance exceeds 500mA per JEDEC standard JESD-17
• Green product and no Sb/Br