Микросхема HEF4028BT.653, Логический элемент дешифратор [SO-16]

Характеристики

HEF4028BT.653, Логический элемент дешифратор [SO-16]The HEF4028BT is a 4-bit BCD to Decimal Decoder with an active low enable or an 8-output (Y0 to Y7) inverting demultiplexer. The outputs are fully buffered for best performance. When used as a BCD to decimal decoder a 1-2-4-8 BCD code applied to inputs A0 to A3 causes the selected output to be high. The other nine outputs will be low. To use the HEF4028B as a BCO to octal decoder, input A3 is an active low enable pin and outputs Y8 and Y9 are not used. A 1-2-4 BCO code applied to inputs A0 to A2 causes the selected output (Y0 to Y7) to be high. The other seven outputs will be low. When A3 is high outputs (Y0 to Y7) will be forced low. When used as an 8-output (Y0 to Y7) inverting demultiplexer A0 to A2 are used as address inputs and A3 is the data input. Outputs Y8 and Y9 are not used. It operates over a recommended VDD power supply range of 3 to 15V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS or another input.

• Fully static operation
• Standardized symmetrical output characteristics
• Complies with JEDEC standard JESD 13-B